Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a system and a semiconductor device for identifying stacked chips by using a through-chip via, and a method thereof.
There has been a continuing demand for high-speed, high-density and low-power semiconductor devices, and the integration density of the semiconductor devices has accordingly increased by scaling-down elements to reduce the linewidth (critical dimension). However, since such a method has limitations, various types of stacked package technologies are developed.
FIG. 1 is a view illustrating a conventional multi die package (MDP) with stacked semiconductor chips.
Referring to FIG. 1, an MDP is configured in such a way as to arrange a pad at an edge in a semiconductor device by using a redistributed layer (RDL) and connect a substrate and the edge electrically by using a wire. Here, a different input may be applied from the substrate to each semiconductor chip, and input/output signals of stacked semiconductor chips may be shared or used independently by the semiconductor chips.
In this manner, in a three-dimensional stacked DRAM package (hereinafter referred to as ‘3DS’), stacked semiconductor chips are interconnected by using an RDL along the edge of each semiconductor chip. Such an edge interconnection may somewhat increase the length and width of the package and need a spare interposer layer between the semiconductor chips. That is, when semiconductor chips are stacked in a package state, a space for wire connection is to be between a pad and a terminal and an interlayer such as an interposer layer is to be inserted between the chips. Therefore, while being advantageous over the case of packaging each semiconductor chip and connecting the semiconductor chip packages in a two-dimensional structure, the case of stacking semiconductor chips in a package state is disadvantageous in terms of the footprint due to an increase in the form factor.
Also, in the above-described chip packaging method, pads may be connected by a gold wire, thus causing a hetero-metal junction. Therefore, the above-described chip packaging method may decrease a data transfer rate and cause a signal skew between stacked dies. The power consumption may be increased due to heat and a signal delay by a parasitic resistance caused at a contact point. Also, in the above-described chip packaging method, when semiconductor chips are stacked by using a wire bonding structure, various concerns may be caused in signal integrity (SI) characteristics.
The technology of a 3DS method for directly stacking semiconductor chips by using a through-chip via is being actively developed to address the above concerns of the MDP using a wire bonding structure.
A through-chip via is also referred to as a through-silicon via (TSV) because a semiconductor chip is generally fabricated using a silicon wafer.
Such a through-silicon via (TSV) is to transfer an internal signal between stacked semiconductor chips. The through-silicon via (TSV) is formed by forming a via (vertical interconnect access) passing through the silicon in a semiconductor chip and filling the via with a conductor (e.g., copper) to form an electrode.
FIG. 2 is a view illustrating a conventional 3DS structure with semiconductor chips stacked by using a through-chip via.
Referring to FIG. 2, a semiconductor device includes a master chip CHIP_1 disposed at the bottom thereof, and a plurality of slave chips CHIP_2 to CHIP_N stacked on the master chip CHIP_1. The master chip CHIP-1 buffers an external signal received from an external control unit, and controls the slave chips CHIP_2 to CHIP_N. The slave chips CHIP_2 to CHIP_N are physically/electrically connected through a through-silicon via TSV to the master chip CHIP_1.
The master chip CHIP_1 transfers a command CMD through the through-silicon via TSV to a semiconductor chip selected from the slave chips CHIP_2 to CHIP_N, and receives an output signal DATA of the selected semiconductor chip through the through-chip via TSV.
However, a problem may arise if the slave chips CHIP_2 to CHIP_N of the same type transmit/receive signals simultaneously.
That is, unless an identification (ID) is given to each of the slave chips CHIP_2 to CHIP_N, it is difficult to determine which of the slave chips CHIP_2 to CHIP_N is to receive a signal transmitted by the master chip CHIP_1 and which of the slave chips CHIP_2 to CHIP_N has transmitted a signal received by the master chip CHIP_1.
FIG. 3 is a view illustrating a conventional method for identifying each semiconductor chip in an MDP.
Referring to FIG. 3, an external signal is applied to each of dies DIE0-DIE3 in an MDP. The dies DIED-DIES have different IDs depending on the corresponding external signals inputted thereto, so that the dies DIE0-DIE3 are identified as different dies DIE0-DIE3. Herein, an RDL is used to form a pad on the edge of each die, and a wire is used to connect a substrate and each pad independently according to the bonding option, where the RDL and wire are used to transmit the external signal.
However, this conventional method may cause a cost increase because a wire bonding structure is used to apply an external signal to each die in the MDP. In particular, if the conventional method is applied to a semiconductor device based on a TSV structure, because the TSV-based semiconductor device has a large number of semiconductor chips stacked therein and may have no edge region for forming a pad, the edge region is to be secured, which may cause disadvantage in terms of the form factor. Therefore, there are demands for a different type of chip-identifying method in the TSV-based semiconductor device.